HDMI Test Report
Overall Results:7
of
13
Tests Failed
| Test Configuration Details |
| Device Description |
| HDMI Test Type | TMDS Physical Layer Tests |
| HDMI Specification | 2.0 |
| Test Session Details |
| Infiniium SW Version | 04.50.0008 |
| Infiniium Model Number | DSOX93204A |
| Infiniium Serial Number | MY53180105 |
| Application SW Version | 1.99.9025 |
| Debug Mode Used | Yes |
| Probe (Channel 1) | Model: 1169A
Serial: US44000259
Head: N5380A/B
Atten: Not Calibrated, Using Default Atten (2.2029E+000)
Skew: Not Calibrated, Using Default Skew |
| Probe (Channel 2) | Model: 1169A
Serial: US49412951
Head: N5380A/B
Atten: Not Calibrated, Using Default Atten (2.2029E+000)
Skew: Not Calibrated, Using Default Skew |
| Probe (Channel 3) | Model: 1169A
Serial: US44000715
Head: N5380A/B
Atten: Not Calibrated, Using Default Atten (2.2949E+000)
Skew: Not Calibrated, Using Default Skew |
| Last Test Date | 2013-09-10 15:33:56 UTC -07:00 |
Summary of Results
|
| Warning | <
5
% |
| Critical | <
2
% |
Report Detail
Test Summary:
FAIL
Test Description:
2 Channels Connection Model: TMDS differential clock jitter must not exceed 0.25*Tbit, relative to the ideal Recovery Clock. For compliance, the DUT should output 27MHz(or 25MHz), 74.25MHz, 148.5MHz, and 222.75MHz for testing.
Test Limits:<= 250 mTbitClock Jitter (Worst of 3 Trials)344 mTbit
# Trials Run:
3
Worst Trial:
Trial 3Result Details:
Overall Summary + details of 3 worst trials|
.
| Trial | Actual Value | Margin | HDMIAutomationConfig | Test Frequency(MHz) | # Edges | Tbit(ps) | Clock Jitter(ps) |
| Avg | 328.0 mTbit | -31.07 % |
| StdDev | 22.40 mTbit | 9.001 % |
| Range | 41.88 mTbit | 16.80 % |
| Min | 302.5 mTbit | -37.60 % |
| Max | 344.4 mTbit | -20.80 % |
| Sum | 984.1 mTbit | -93.20 % |
 | Trial 1 | 302 mTbit | -20.8% | Not defined | 148.557 | 16.000000000 M | 673.143 | 203.620 |
| Trial 2 | 337 mTbit | -34.8% | Not defined | 148.535 | 16.000000000 M | 673.243 | 227.040 |
| Trial 3 (Worst) | 344 mTbit | -37.6% | Not defined | 296.923 | 16.000000000 M | 336.788 | 115.980 |
Trial 1
Trial 1: Clock Jitter
Trial 2
Trial 2: Clock Jitter
Trial 3
Trial 3: Clock Jitter
Test Summary:
Pass
Test Description:
2 Channels Connection Model: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psRaw Clock Transition Time (Worst of 2 Trials)84.239 ps
# Trials Run:
2
Worst Trial:
Trial 2Result Details:
Overall Summary + details of 2 worst trials|
.
| Trial | Actual Value | Margin | HDMIAutomationConfig | Test Frequency(MHz) | Upper Threshold(%) | Lower Threshold(%) | # Edges |
| Avg | 84.38 ps | 12.50 % |
| StdDev | 193.0 mps | 257.4 m% |
| Range | 273.0 mps | 364.0 m% |
| Min | 84.24 ps | 12.32 % |
| Max | 84.51 ps | 12.68 % |
| Sum | 168.8 ps | 25.00 % |
 | Trial 1 | 84.512 ps | 12.7% | Not defined | 148.557 | 80.000 | 20.000 | 10.995000 k |
| Trial 2 (Worst) | 84.239 ps | 12.3% | Not defined | 296.923 | 80.000 | 20.000 | 11.003000 k |
Trial 1
Trial 1: Raw Clock Transition Time
Trial 2
Trial 2: Raw Clock Transition Time
Test Summary:
Pass
Test Description:
2 Channels Connection Model: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psRaw Clock Transition Time (Worst of 2 Trials)82.745 ps
# Trials Run:
2
Worst Trial:
Trial 1Result Details:
Overall Summary + details of 2 worst trials|
.
| Trial | Actual Value | Margin | HDMIAutomationConfig | Test Frequency(MHz) | Upper Threshold(%) | Lower Threshold(%) | # Edges |
| Avg | 82.78 ps | 10.37 % |
| StdDev | 50.91 mps | 67.88 m% |
| Range | 72.00 mps | 96.00 m% |
| Min | 82.75 ps | 10.33 % |
| Max | 82.82 ps | 10.42 % |
| Sum | 165.6 ps | 20.75 % |
| Trial 1 (Worst) | 82.745 ps | 10.3% | Not defined | 148.557 | 80.000 | 20.000 | 10.995000 k |
| Trial 2 | 82.817 ps | 10.4% | Not defined | 296.923 | 80.000 | 20.000 | 11.003000 k |
Trial 1
Trial 1: Raw Clock Transition Time
Trial 2
Trial 2: Raw Clock Transition Time
Test Summary:
Pass
Test Description:
2 Channels Connection Model: Clock duty cycle must be at least 40% and not more than 60%.The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>=40%Clock Duty Cycle Minimum (Worst of 2 Trials)49.610
# Trials Run:
2
Worst Trial:
Trial 1Result Details:
Overall Summary + details of 2 worst trials|
.
| Trial | Actual Value | Margin | HDMIAutomationConfig | Test Frequency(MHz) | # Edges | TdutyMIN(ns) |
| Avg | 49.72 | 24.29 % |
| StdDev | 148.5 m | 371.2 m% |
| Range | 210.0 m | 525.0 m% |
| Min | 49.61 | 24.03 % |
| Max | 49.82 | 24.55 % |
| Sum | 99.43 | 48.58 % |
| Trial 1 (Worst) | 49.610 | 24.0% | Not defined | 148.557 | 10.000000 k | 3.339 |
| Trial 2 | 49.820 | 24.6% | Not defined | 296.923 | 10.000000 k | 1.678 |
Trial 1
Trial 1: Clock Duty Cycle Minimum
Trial 2
Trial 2: Clock Duty Cycle Minimum
Test Summary:
Pass
Test Description:
2 Channels Connection Model: Clock duty cycle must be at least 40% and not more than 60%.The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:<=60%Clock Duty Cycle Maximum (Worst of 2 Trials)50.280
# Trials Run:
2
Worst Trial:
Trial 2Result Details:
Overall Summary + details of 2 worst trials|
.
| Trial | Actual Value | Margin | HDMIAutomationConfig | Test Frequency(MHz) | # Edges | TdutyMAX(ns) |
| Avg | 50.26 | 16.24 % |
| StdDev | 35.36 m | 58.93 m% |
| Range | 50.00 m | 83.33 m% |
| Min | 50.23 | 16.20 % |
| Max | 50.28 | 16.28 % |
| Sum | 100.5 | 32.48 % |
| Trial 1 | 50.230 | 16.3% | Not defined | 148.557 | 10.000000 k | 3.381 |
| Trial 2 (Worst) | 50.280 | 16.2% | Not defined | 296.923 | 10.000000 k | 1.693 |
Trial 1
Trial 1: Clock Duty Cycle Maximum
Trial 2
Trial 2: Clock Duty Cycle Maximum
Test Summary:
FAIL
Test Description:
For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:No Mask FailuresTotal # failures (Worst of 3 Trials)88.890000 k
# Trials Run:
3
Worst Trial:
Trial 3Result Details:
Overall Summary + details of 3 worst trials|
.
| Trial | Actual Value | Margin | Maximum Margin (s) | Maximum Margin (Vertical) (V) | HDMIAutomationConfig | Eye Width(ps) | Eye Height(mV) | Data Lane A | Test Frequency(MHz) | Mask Moved(ps) | # Acquisitions Point | Tbit(ps) | RightJitterData(Tbit) | LeftJitterData(Tbit) | RightJitterData(ps) | LeftJitterData(ps) | Differential Swing Voltage(V) |
| Avg | 31.63 k | -3.162 M% | -40.86 ps | 0.000 V |
| StdDev | 49.68 k | 4.968 M% | 28.82 ps | 0.000 V |
| Range | 88.80 k | 8.880 M% | 54.15 ps | 0.000 V |
| Min | 89.00 | -8.889 M% | -73.64 ps | 0.000 V |
| Max | 88.89 k | -8.850 k% | -19.49 ps | 0.000 V |
| Sum | 94.88 k | -9.487 M% | -122.6 ps | 0.000 V |
| Trial 1 | 5.897000 k | -590E+03% | -74 ps | 0.000000000000 V | Not defined | 409.500 | 0.000 | D0 | 148.557 | 73.600 | 16.000000000 M | 673.446 | 392 m | 385 m | 264.000 | 259.500 | 991 m |
| Trial 2 | 89.000 | -885E+01% | -29 ps | 0.000000000000 V | Not defined | 450.000 | 348.380 | D0 | 148.479 | 29.500 | 16.000000000 M | 673.428 | 330 m | 325 m | 222.000 | 219.000 | 988 m |
| Trial 3 (Worst) | 88.890000 k | -889E+04% | -19 ps | 0.000000000000 V | Not defined | 3.720 | 0.000 | D0 | 296.923 | 19.500 | 16.000000000 M | 336.706 | 608 m | 984 m | 204.720 | 331.280 | 986 m |
Trial 1
Trial 1: Total # failures
Trial 2
Trial 2: Total # failures
Trial 3
Trial 3: Total # failures
Test Summary:
FAIL
Test Description:
For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:<=0.3TbitTbitCheck (Worst of 3 Trials)984 m
# Trials Run:
3
Worst Trial:
Trial 3Result Details:
Overall Summary + details of 3 worst trials|
.
| Trial | Actual Value | Margin | HDMIAutomationConfig | Data Lane A | Test Frequency(MHz) | Mask Moved(ps) | # Acquisitions Point | Tbit(ps) | RightJitterData(Tbit) | LeftJitterData(Tbit) | RightJitterData(ps) | LeftJitterData(ps) | Differential Swing Voltage(V) |
| Avg | 568.5 m | -89.56 % |
| StdDev | 361.1 m | 120.3 % |
| Range | 654.2 m | 218.0 % |
| Min | 329.7 m | -228.0 % |
| Max | 983.9 m | -10.00 % |
| Sum | 1.706 | -268.7 % |
| Trial 1 | 392 m | -30.7% | Not defined | D0 | 148.557 | 73.600 | 16.000000000 M | 673.446 | 392 m | 385 m | 264.000 | 259.500 | 991 m |
| Trial 2 | 330 m | -10.0% | Not defined | D0 | 148.479 | 29.500 | 16.000000000 M | 673.428 | 330 m | 325 m | 222.000 | 219.000 | 988 m |
| Trial 3 (Worst) | 984 m | -228.0% | Not defined | D0 | 296.923 | 19.500 | 16.000000000 M | 336.706 | 608 m | 984 m | 204.720 | 331.280 | 986 m |
Trial 1
Trial 1: TbitCheck
Trial 2
Trial 2: TbitCheck
Trial 3
Trial 3: TbitCheck
Test Summary:
Pass
Test Description:
The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psTransition Time (Worst of 2 Trials)81.326 ps
# Trials Run:
2
Worst Trial:
Trial 1Result Details:
Overall Summary + details of 2 worst trials|
.
| Trial | Actual Value | Margin | HDMIAutomationConfig | Test Frequency(MHz) | Data Lane A | Upper Threshold(%) | Lower Threshold(%) | #Edge |
| Avg | 82.07 ps | 9.432 % |
| StdDev | 1.058 ps | 1.410 % |
| Range | 1.497 ps | 1.995 % |
| Min | 81.33 ps | 8.435 % |
| Max | 82.82 ps | 10.43 % |
| Sum | 164.1 ps | 18.86 % |
| Trial 1 (Worst) | 81.326 ps | 8.4% | Not defined | 148.557 | D0 | 80.000 | 20.000 | 18.941000 k |
| Trial 2 | 82.822 ps | 10.4% | Not defined | 296.923 | D0 | 80.000 | 20.000 | 21.732000 k |
Trial 1
Trial 1: Transition Time
Trial 2
Trial 2: Transition Time
Test Summary:
Pass
Test Description:
The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psTransition Time (Worst of 2 Trials)76.554 ps
# Trials Run:
2
Worst Trial:
Trial 2Result Details:
Overall Summary + details of 2 worst trials|
.
| Trial | Actual Value | Margin | HDMIAutomationConfig | Test Frequency(MHz) | Data Lane A | Upper Threshold(%) | Lower Threshold(%) | #Edge |
| Avg | 77.28 ps | 3.043 % |
| StdDev | 1.030 ps | 1.373 % |
| Range | 1.456 ps | 1.941 % |
| Min | 76.55 ps | 2.072 % |
| Max | 78.01 ps | 4.013 % |
| Sum | 154.6 ps | 6.085 % |
| Trial 1 | 78.010 ps | 4.0% | Not defined | 148.557 | D0 | 80.000 | 20.000 | 18.960000 k |
| Trial 2 (Worst) | 76.554 ps | 2.1% | Not defined | 296.923 | D0 | 80.000 | 20.000 | 21.732000 k |
Trial 1
Trial 1: Transition Time
Trial 2
Trial 2: Transition Time
Test Summary:
FAIL
Test Description:
For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:No Mask FailuresTotal # failures88.890000 kResult Details:
Result Details
HDMIAutomationConfigNot definedData Lane AD1Test Frequency(MHz)296.923Mask Moved(ps)19.500# Acquisitions Point16.000000000 MTbit(ps)336.706RightJitterData(Tbit)608 mLeftJitterData(Tbit)984 mRightJitterData(ps)204.720LeftJitterData(ps)331.280Differential Swing Voltage(V)986 mTrial 1
Trial 1: Total # failures
Test Summary:
FAIL
Test Description:
For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:<=0.3TbitTbitCheck984 mResult Details:
Result Details
HDMIAutomationConfigNot definedData Lane AD1Test Frequency(MHz)296.923Mask Moved(ps)19.500# Acquisitions Point16.000000000 MTbit(ps)336.706RightJitterData(Tbit)608 mLeftJitterData(Tbit)984 mRightJitterData(ps)204.720LeftJitterData(ps)331.280Differential Swing Voltage(V)986 mTrial 1
Trial 1: TbitCheck
Test Summary:
FAIL
Test Description:
The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psTransition Time70.807 psResult Details:
Result Details
HDMIAutomationConfigNot definedTest Frequency(MHz)296.923Data Lane AD1Upper Threshold(%)80.000Lower Threshold(%)20.000#Edge21.759000 kTrial 1
Trial 1: Transition Time
Test Summary:
FAIL
Test Description:
The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psTransition Time68.073 psResult Details:
Result Details
HDMIAutomationConfigNot definedTest Frequency(MHz)296.923Data Lane AD1Upper Threshold(%)80.000Lower Threshold(%)20.000#Edge21.757000 kTrial 1
Trial 1: Transition Time
